Terasic DE2-70 Board

[nunya_bizness]

Well I got Asteroids working on the board :), PACMAN shows a screen but is hung. :confused:
FYI.. several differences from the DE2 is frustrating (pin name/assignment changes, use of Sync SRAM (not Async like the normal DE2). I am still diggin' thru the codebase to get the full gist of the PACE framework.
Should I change the current DE code to handle the DE2-70 as a subset of the DE2, or just start a new target?
Also should I generate a "SDRAM as SRAM" core, [or even modify the code to make a "SSRAM as SRAM" core] for the platforms that use external SDRAM?[I guess that core could go in the stubs folder. Just seeing how to proceed for submission of code...Thoughts?

[tcdev]

PACMAN shows a screen but is hung. :confused:That one should've been quite straight-forward... only difference to de2 project should be target_top... and perhaps the input clock??? I should check that it still runs on the de2 tomorrow... I'll post here if I find a problem...

Should I change the current DE code to handle the DE2-70 as a subset of the DE2, or just start a new target?Definitely start a new target. Something like de2-70...

Also should I generate a "SDRAM as SRAM" core, [or even modify the code to make a "SSRAM as SRAM" core] for the platforms that use external SDRAM?[I guess that core could go in the stubs folder. Just seeing how to proceed for submission of code...Thoughts?SDRAM as SRAM would be nice, feel free to go ahead. It's something I've considered. MikeJ has done a similar core for his "Replay" board I believe.

Since each SDRAM controller is potentially different, I'd add the implementation in the target (de2-70) directory. Have to see how the rest pans out... I've only just started adding SDRAM to the projects, so I'm not 100% sure how I'm going to handle it. Probably use a different "sdram_pkg.vhd" file for different SDRAM controllers... hence the copy in the "stubs" directory currently. The only other project using (PACE) SDRAM is the NeoGeo, which uses the yadmc controller with wishbone i/f.

[tcdev]

Was configured to use external SRAM.

I've updated the project_pkg to use internal ram for CPU ram, and confirmed it runs on the DE2.

[nunya_bizness]

Thanks.
Still debating on using this SDRAM core [http://www.cmosexod.com/sdram.html] as a base, since its interface is like that of a typical SRAM. Just need to work out the hand-shaking between the host and the SDRAM core somehow.. [it's done through the "sdram_busy_l" signal generated by the core] Might just be lazy for now and reconfigure to do the SRAMs internally since I have 1.1 Mbits of RAM available on board the 2C70...
Learned quite a bit so far about making the HDL device independant from PACE...this beats boring tutorials!

[nunya_bizness]

Here's my DE2-70 target files. I've been copying the DE2 synth folder per platform and editing as needed(device,pin assigns, etc) I have noticed some settings in the de2 synth[platforms].qsfs that don't match the actual svn source file paths...two entries go too deep...
set_global_assignment -name VERILOG_FILE ../../../../../src/target/de2/I2C_Controller.v
set_global_assignment -name VERILOG_FILE ../../../../../src/target/de2/I2C_AV_Config.v

[tcdev]

Here's my DE2-70 target files.
Cool, thanks! I've added them to the repository! Feel free to add some platform project files as well!

I have noticed some settings in the de2 synth[platforms].qsfs that don't match the actual svn source file paths...two entries go too deep...
set_global_assignment -name VERILOG_FILE ../../../../../src/target/de2/I2C_Controller.v
set_global_assignment -name VERILOG_FILE ../../../../../src/target/de2/I2C_AV_Config.v
Yeah, there's a few "cut and paste" errors in there, though it still builds! I only find them when double-clicking in the project file pane to open the files. Then I correct them.

[nunya_bizness]

Heres a few...
Asteroids..graphics flicker a bit..but as much as the original from what I remember!
Pacman-no sound...:(

I am working on C64 and CoCo for giggles...can't get anything to synth but I'm working on it.. :D
Where can I get more technical info on your p2a, and the actual external interface pinout for JAMMA and the LCD for the DE2? I disabled the outputs to the GPIO for the DE2-70 since I dont have either and don't feel comfortable enabling them at this point since I cant test 'em. :o

Hopefully I'll run into someone else w/ a DE2-70..figuring out a good wrapper that works across the board in PACE to use the SSRAM without breaking stuff is driving me bonkers...oh well. I'll add stuff as i go.

[tcdev]

Heres a few...
Asteroids..graphics flicker a bit..but as much as the original from what I remember!
Asteroids will flicker quite a bit - the "phosphor decay" simulation is extremely crude to fit in the limited amount of internal RAM.:D

I am working on C64 and CoCo for giggles...can't get anything to synth but I'm working on it.. :D
Not sure what state I left those 2 projects in...:o

Where can I get more technical info on your p2a, and the actual external interface pinout for JAMMA and the LCD for the DE2? I disabled the outputs to the GPIO for the DE2-70 since I dont have either and don't feel comfortable enabling them at this point since I cant test 'em. :oTo follow...

[tcdev]

Where can I get more technical info on your p2a, and the actual external interface pinout for JAMMA and the LCD for the DE2?
Umm, what do you need to know about P2A? It's a proprietary platform so there's no technical information publically available. It's a little confusing because I maintained the original FPGA pin names in target_top but added a PACE-specific daughterboard, using aliases for some of the signals. It was never meant for "public consumption" :D

As for JAMMA, there's no standard external interface pinout. All 'JAMMA' signals are emulated via PS/2 keyboard and/or DC/NGC controller interfaces. The JAMMA signals themselves are internal to PACE.

The LCD interface is documented in the LCD user guide which is available download from the TerASIC website here (http://www.terasic.com.tw/attachment/archive/78/TRDB_LCM_UserGuide_061130.pdf).

You may need to ask me more specific questions about P2A etc... I'm guessing the GPIO on Coco/C64 is causing you some grief???

[nunya_bizness]

It's a proprietary platform so there's no technical information publically available. It's a little confusing because I maintained the original FPGA pin names in target_top but added a PACE-specific daughterboard, using aliases for some of the signals. It was never meant for "public consumption" :D
This info actually sets me straight on a few things..Thanks.

All 'JAMMA' signals are emulated via PS/2 keyboard and/or DC/NGC controller interfaces. The JAMMA signals themselves are internal to PACE.
I wasn't too far off ... [I'm smarter than I thought]...

The LCD interface is documented in the LCD user guide which is available download from the TerASIC website here (http://www.terasic.com.tw/attachment/archive/78/TRDB_LCM_UserGuide_061130.pdf).
I thought so... [wow right for once...]

You may need to ask me more specific questions about P2A etc... I'm guessing the GPIO on Coco/C64 is causing you some grief??? Not really...just digging deeper and looking for general details(if there is such a thing!) ... [I realize I have some more research and learning to do... :o]
If I have anything more specific..I'll ask..
Thanks!

[RedskullDC]

Hi Nunya_biz,


Hopefully I'll run into someone else w/ a DE2-70...

There are now at least 2 of us with a DE2-70 on here..:)

Cheers,
Red

[nunya_bizness]

Hi Nunya_biz,



There are now at least 2 of us with a DE2-70 on here..:)

Cheers,
Red

I don't feel so lonely. ;)Feel free to comment on anything I submit!
[BTW I have the C64 synthesized and running but has a intermittent VGA signal dropout on a LCD monitor...I haven't had time to adjust timings from the original DE2 source...:(] The extra space in the FPGA is nice but the subtle differences are making learning VHDL/Verilog along with how to best integrate changes for the DE2-70 into PACE a pain ... :rolleyes:

[tcdev]

[BTW I have the C64 synthesized and running but has a intermittent VGA signal dropout on a LCD monitor...I haven't had time to adjust timings from the original DE2 source...:(]
That could be a C64 core problem. The current design is based on Peter's C-One core, which apparently plays silly-buggers with the VGA HSYNC timing to get the CPU core frequency right. I can't get it to sync on a DVI monitor, for example. Blecckkk!! :eek:

[RedskullDC]

Hi Nunya_bizness, et al.
The extra space in the FPGA is nice but the subtle differences are making learning VHDL/Verilog along with how to best integrate changes for the DE2-70 into PACE a pain ... :rolleyes:

What subtle differences?

Could be worse..you could be targeting Xilinx :eek:

We were tooling around with a couple of DE2-70's at our computer meet yesterday, using your target top to get a few more platforms going.

Just about to upload them now...

Cheers,
Red

[tcdev]

A note on the repository.

The idea is not to check in the (unzipped) contents of ported projects. eg. Asteroids.

The SVN repository contains a copy of the zip file(s) only - after checking out you need to unzip the archive locally into an "unzip" folder.

The reason for this is to facilitate updates of the ported projects. For example, if an update of Asteroids is released, the zip archive is added to SVN and you would then overwrite your local copy in the "unzip" directory. If all goes well, you could simply build the new version from there without any other changes. Of course, it may be that the update requires changes to PACE, but that won't always be the case.

It also clearly delineates what comprises the "PACE" components of a ported project, and help to ensure that PACE-specific changes are not "lost" in files overwritten by new releases from the original author.

[RedskullDC]

Hi tcdev,
A note on the repository.

The idea is not to check in the (unzipped) contents of ported projects. eg. Asteroids.
.

Sorry about that! My bad. (raps self over the knuckles with steel ruler).

Will avoid this in future.

Cheers,
leslie

[tcdev]

Will avoid this in future.
No problem!

[nunya_bizness]

What subtle differences?


The board component changes from the old DE-2 to the DE2-70 (for example SRAM to SSRAM) and other "minor" stuff that makes the plethora of the standard DE2 HDL examples found on the web incompatable with the DE2-70 out of the box....but the icing on the cake was that the DE2-70 Control Panel app (new version) craps out 1/2 the time on me...It is just a general ranting type comment about the amount of fustration I had to deal with as a FPGA virgin to just get a feel about the board and get comfortable with Verilog/VHDL...but after a month or two...it actually makes the learning stick in my grey matter for good ..... :cool: